![]() ![]() ![]() The following tables show the address offset for the design example and client logic at the top-level of the design. ![]() Table 2: Interfacesignals.png (Click here for image)Īll register space for this example design is 32 bit. When the master_reset_n is asserted, it brings down all modules in the design example.įigure 1: Clock%26reset_scheme.png (Click here for image) This reset signal is then synced to different clock domain internally. The master reset is asynchronous and active low reset signal. At the top-level of the design, there are two external clock sources, ref_clk_clk (322.265625MHz) and csr_clk (100MHz)and one master reset, master_reset_n. The following diagram shows the clocking and reset scheme for the design example. Table 1: Table1.png (Click here for image) Refer to Design Examples for Low Latency 10G Ethernet MAC User Guide for more information. User can apply the "10GBase-R Register Mode Example Design" preset at the right bottom corner of Low Latency Ethernet 10G MAC IP Parameter Editor to generate this design example. Note: This design example can be generated from the Low Latency Ethernet 10G MAC IP Parameter Editor of which can be invoked from IP Catalog beginning with Quartus Prime v15.1. Scalable LL Ethernet 10G MAC with 10G BaseR PHY Design Example Single Port LL Ethernet 10G MAC with 1588 using Native PHY Design Exampleģ. AN701:Scalable Low Latency Ethernet 10G MAC using Arria 10 1G/10G PHYĢ. Other Low Latency Ethernet 10G MAC reference designs:ġ. Besides,it supports packet monitoring system on transmit and receive paths and report Ethernet MAC statistics counter for transmit and receive data paths. It is capable to achieve low roundtrip latency, 136.677ns (time taken to transmit the first data from Avalon-ST TX interface to be available at Avalon-ST RX interface) in the simulation. This design example demonstrates Low Latency 10G Ethernet IP solution for Arria 10® using Altera® Low Latency 10-Gbps Ethernet (10GbE) Media Access Controller (MAC) and Native PHY IP cores with small form factor pluggable plus (SFP+). Low Latency Ethernet 10G MAC using Arria 10 PHY 10GBASE-R Register Mode ![]()
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